This invention relates to a semiconductor device suitable for resolving problems, such as large spike current arising when the power supply is switched-on or due to voltage fluctuations during operation, erroneous operation, etc. in the semiconductor device.
It is known that in semiconductor devices, during a certain period of time from the switch-on of the power supply to stabilization in the normal operation state, since the state in the interior of the semiconductor devices is different from the normal operation state, various problems can be produced. One of the most important problems among those arising at the moment of the switch-on of the power supply is production of a large spike current, which can eventually break down the power supply equipment for operating semiconductor devices or the semiconductor devices themselves. The outline of the mechanism giving rise to this spike current will be approximately explained, referring to FIGS. 1A and 1B.
FIG. 1A shows schematically a cross-sectional structure of main parts in an MOS dynamic random access memory (hereinbelow abbreviated to DRAM). Here is shown an example of DRAMs incorporating a back bias generator in the chip, forming the main current in recent DRAMs. Further, the shown example uses a so-called one-transistor-type cell, for which a memory storing one-bit information consists of an MOS transistor acting as a switching device and a capacitor for accumulating information charge. In the figure, the reference numeral 300 indicates the on-chip back bias generator state above. Although the generator 300 is indicated for convenience as separated from the chip, which is a silicon substrate 1, and as a circuit schematic, in reality it is of course disposed principally in the surface portion of the substrate 1 or integrated in its neighborhood. The circuit construction shown within a frame in chain-dotted line indicated by 300 is an example, where the back bias V.sub.BB is generated by the well known charge pumping method, in which OSC denotes a circuit for producing a cyclic signal for the charge pumping, which consists usually of a ring oscillator circuit. C.sub.PB represents a capacitor for the charge pumping, which is formed in many cases by utilizing an MOS capacitor. D indicates a rectifying diode, for which, in many cases, an MOS transistor is used as a diode by connecting the drain and the gate together. This circuit construction and its working mode are described in detail in 1976 ISSCC Digest of Technical Papers, pp. 138-139.
The reference numeral 1 represents the silicon substrate, which is a p-conductivity type silicon substrate, in the case where the principal element constituting the circuit is an n-channel MOS transistor and an n-conductivity type silicon substrate, in the case where the principal element constituting the circuit is a p-channel MOS transistor. However, here an example for the former case will be explained. The reference numeral 2 indicates an insulating film for isolating different elements. Numerals 3a-3b denote relatively high concentration n-conductivity type (hereinbelow called n.sup.+ type) impurity diffusion layers; and 4a-4c denote gate electrodes, which are made of polysilicon, refractory metal such as Al, W, Mo, etc., or silicide such as WSi.sub.2, MoSi.sub.2, etc. The gate electrodes 4a-4c can be fabricated, according to circumstances, by a different fabrication step or they can be made of another material. Although there exist gate insulating films between the gate electrodes 4a-4c and the substrate 1, they are not shown in the figure for the sake of clarity.
The gate electrode 4a, and the impurity diffusion layers 3a and 3b constitute a switching MOS for a memory cell. The reference numeral 4b is an electrode of storage capacitor (hereinbelow called a plate electrode) and a capacitor is formed between this electrode and the inversion layer 5 produced directly below the electrode. The insulating film existing between the electrode 4b and the inversion layer and acting as a dielectric body is not indicated in the figure, as stated above. The gate electrode 4c, the impurity diffusion layers 3d and 3e also constitute an MOS transistor, which is indicated as a representative of MOS transistors constituting a circuit other than the memory cell.
In the figure, the reference numerals 7 and 8 show the approximate domain classification within the memory chip, in which numeral 7 indicates the memory cell array portion and 8 the peripheral circuit portion controlling the work of the memory cell array. Both the portions 7 and 8 are composed of course of a plurality of circuits consisting of a plurality of memory cells and a plurality of MOS transistors, respectively.
Now, in a memory chip described above, large spike current at the moment of the switch-on of the power supply is produced principally by the following two mechanisms.
Firstly, during a period of time just after the switch-on of the power supply, when the back bias generator circuit doesn't yet work satisfactorily, since the back bias voltage V.sub.BB is lower than the normal value (the absolute value is small), the threshold voltage of the MOS transistor composed of the impurity diffusion layers 3d and 3e and the gate electrode 4c, etc. is negative. Due to this fact, spike current arises from the power supply V.sub.CC to ground. That is, as indicated in FIG. 1B, the back bias generator circuit doesn't work, until the power supply voltage V.sub.CC reaches a certain voltage V.sub.crt. Consequently, since the voltage V.sub.BB is almost 0 V and the threshold voltage of the MOS transistor is negative according to circumstances, spike current arises. These phenomena are described in 1980 ISSCC Digest of Technical Papers, pp. 228-229.
Another production mechanism for spike current is due to capacitor coupling between the power supply and the silicon substrate. This phenomenon has become an important problem, particularly in recent years, because parasitic capacity between the power supply and the substrate increases with increasing packing density of the memory. It is the spike current provoked by the parasitic capacity C.sub.PS between the plate electrode 4b and the substrate that has the most important influences. The peak value I.sub.P of the current I.sub.CC from the power supply is represented by ##EQU1## When the value of the capacity C.sub.PS becomes very great due to the increase in the packing density of the memory, the displacement current between the power supply V.sub.CC and the substrate through the capacity C.sub.PS also becomes extremely great. The more rapidly the voltage of the power supply rises, the greater I.sub.P is. The two sorts of current described above are observed as spike current at the moment when the power supply is switched-on and at the same time the following phenomenon is produced and further increases spike current. That is, in a DRAM including the back bias generator in the chip, since the driving capability of the back bias generator is low by nature and in addition the back bias generator doesn't work normally just after the switch-on of the power supply, the substrate 1 is almost in a floating state. Consequently, when current flows through the capacity C.sub.PS, the voltage V.sub.BB rises in the positive direction, as indicated by a broken line in FIG. 1B. As the result the threshold voltage of the MOS transistor stated above is displaced in the negative direction, which produces at the same time the following phenomenon giving rise to a still more important problem. That is, n.sup.+ type diffusion layers, such as 3c and 3e, and the p-conductivity type substrate 1 are forward biased and parasitic bipolar transistors as indicated by Q.sub.1 and Q.sub.2 act as active devices. In this case, currents as indicated by I.sub.Q1 and I.sub.Q2 flow, which increases further the spike current in addition to the displacement current described above. That is, the current produced by the capacity C.sub.PS is the base current therefor. Consequently, the current flowing between collector and emitter is h.sub.fe (current gain) times as large as the base current and depends considerably on h.sub.fe of the parasitic transistors Q.sub.1, Q.sub.2, etc. Since Q.sub.1 and Q.sub.2 are lateral type transistors in this case, this value (h.sub.fe) is relatively small with respect to usual transistors. But h.sub.fe becomes larger and the problem of the spike current becomes more important, as the distance between diffusion layers acting as emitter and collector becomes smaller with increasing packing density.
Although the production mechanism of the spike current at the moment of the switch-on of the power supply has been explained above by using a DRAM as an example, the problem of the spike current described above is more important for the case of DRAM, in which both a p-channel MOS transistor and a n-channel MOS transistor are used as principal constituent elements, so-called CMOS type.
At the moment of the switch-off of the power source the back bias varies further toward negative by the capacitor coupling, as indicated in FIG. 1B. However, this does not particularly influence the spike current, subject to be treated here. Consequently, in the following figures, waveforms at the moment of the switch-off of the power source and also their explanation will be omitted.
FIG. 2A is a cross-sectional view of the principal part of a CMOS type LSI. The reference numeral 1 indicates a p-conductivity type silicon substrate and 9 represents an n-conductivity type impurity diffusion layer, which is usually called a "well" and in which a p-channel MOS transistor is formed. On the other hand, an n-channel MOS transistor is formed directly in the p-conductivity type silicon substrate 1. Further, there can be cases, in which the silicon substrate is of n-conductivity type; the well is of p-conductivity type; the n-channel MOS transistor is formed in the well; and the p-channel MOS transistor is formed in the substrate. The reference numerals 3f and 3g indicate representatively diffusion layers used as sources or drains of MOS transistors. The former shows an n.sup.+ type diffusion layer and the latter indicates a p.sup.+ type diffusion layer. Such a structure gives rise to n-p-n type and p-n-p type parasitic bipolar transistors, as indicated by Q.sub.3 and Q.sub.4, respectively, and to parasitic resistances as indicated by R.sub.1 and R.sub.2. These are so connected that they are equivalent to a so-called thyristor, as indicated in FIG. 2B. For this reason, once the thyristor goes into the "on" state, layer current flows between the power source V.sub.CC and ground, and finally the element breaks down. This is the so-called latch-up phenomenon in the CMOS type semiconductor device, which is described in detail e.g. in 1982 IEDM, Technical Digest, pp. 454-477. Such a thyristor device is made conductive with a trigger current, which is greater than a certain value, flowing through the base of Q.sub.3 or Q.sub.4. The spike current produced at the moment of the switch-on of the power source stated above acts just as the trigger current and poses an important problem.
It is described in the above-mentioned publication 1980 ISSCC Digest of Technical Papers, pp. 228-229 that among various sorts of spike currents discussed above, those produced by the fact that the threshold voltage of the MOS transistor becomes negative can be reduced to some extent by setting suitable element constants. However, the spike current produced by the capacitor coupling increases more and more with increasing packing density and will be an important problem in the future. In order to resolve this problem, there is known a method by which the potential of the plate electrode 4b in FIG. 1 is changed from V.sub.CC to the ground potential. For this purpose it is necessary to dispose a low concentration n-conductivity type layer just below the plate electrode 4b so that the channel 5 is formed, even when the electrode 4b is at ground potential. As a result, since not only a new fabrication step is necessary, but also additional mask alignment tolerance is necessary for the photolithography process, the effective memory cell size is reduced and the chip size should be enlarged. For this reason, essential problems, such as decrease of production yield, rise of price, etc., are produced.
Although, in the above, the spike current produced at the moment of the switch-on of the power source has been explained, there are problems that also occur during normal operation. For example, spike current can be produced by fluctuations of the power source voltage, or voltage fluctuations can be transmitted, e.g. through the plate electrode 4b in FIG. 1A, to the channel 5. This can also give rise to erroneous operation.